DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an
8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer
at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The
differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input
receiver. DQS is center-aligned with data for WRITEs.
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